Field of the Invention
The present invention relates in general to scan testing latches or registers, and more particularly to a scannable data synchronizer that can successfully latch an asynchronous data signal relative to a clock signal to be registered into a clock domain controlled by the clock signal during normal operation, and that is also scannable for test purposes.
Description of the Related Art
Metastability in a digital system is an undesired condition in which a digital or binary signal temporarily assumes an incorrect or invalid state potentially causing malfunction or circuit failure. A binary signal within a digital system has an invalid state while its signal level (voltage or current) is neither high nor low but in an intermediate voltage range rendering its logic state indeterminate. Metastability may result when there is clock skew or whenever setup and hold time violations occur. A flip-flop may be used to register a data signal into a clock domain. If the data signal is generated from a different clock domain or is an asynchronous signal, then the data signal may change state in violation of the setup and hold time of the flip-flop, such as at or near an operative edge of the clock signal driving the flip-flop. In the event of such a timing violation, the flip-flop may enter a metastable state in which it temporarily enters an incorrect or even invalid state before settling to the correct state.
One conventional solution is to pass the data signal through two registers coupled in series, in which the second register is provided to clean up the signal from the first. The faster the system is operated, however, the more likely that the second register will eventually fail or otherwise register an incorrect value. Another conventional approach is to simply add additional registers in series to further reduce the probability of failure. This approach may be undesirable in many digital circuits because it adds significant latency thus reducing performance.
Another conventional solution relied upon the ability to adjust the relative size or ratio of the drive strength of individual transistors to detect metastablity. Newer technologies, such as quantized FinFET technology, deliver improved levels of scalability and performance at the expense of reduced ability to adjust individual transistor size and drive strength. The techniques employed in the conventional solutions do not guarantee proper operation under all operating conditions using any type of technology including the newer FinFET technologies and the like.
Regardless of the solution, it is also desired that the solution be scannable for test purposes in which the latching or register functions are made available during a scan test mode.